An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application

This article presents a novel approximate adder that is design-optimized and has optimized error metrics. Optimization in design translates into optimization of the parameters such as delay, power, area/resources, metrics points to usefulness proposed for practical applications. We refer hardware having near-normal distribution HOAANED, short. consider implementation HOAANED other adders based on ASIC FPGA environments. used Xilinx Artix-7 device implementation, 32/28-nm CMOS standard digital cell library an implementation. To demonstrate utility we considered image processing application performed experimentation with many images. The quality images reconstructed using was analyzed peak signal-to-noise ratio (PSNR), which qualitative figure-of-merit assess It found achieves improved PSNR comparison processing, this achieved simultaneously featuring characteristics.